# coscope ### The AI copilot for hardware bring-up & debug. It reads your schematic, firmware, and bench instruments at the same time - so a new board comes up in hours, not weeks. *Berlin · Pre-seed · 2026* --- ## 01 - The problem: bringing up a new circuit board is still a manual, undocumented guessing game. When a freshly assembled board hits the bench, a senior engineer ($150–300/hr, fully loaded) has to reconcile three things in their head: - the **schematic & BOM** (what it *should* do) - the **firmware** (what it's *trying* to do) - the **bench instruments** (what it's *actually* doing - scope, logic analyzer, DMM, power supply) No tool holds all three at once. So the engineer works it out by hand - and the only record of *how* survives like this: > "9 out of 10 times, someone snaps a pic with their phone." > - practising EE, Hackaday, 2024 Phone photos → Slack → a Word doc nobody opens again. When the engineer moves on, the knowledge walks out the door. **The three costs:** 1. **Time** - bring-up burns the most expensive minutes in the whole product cycle: senior EE bench time, a major gate at each stage of product development. 2. **Knowledge loss** - Documentation collapses the moment a deadline appears - more time never arrives. > "Single source of truth is the biggest, biggest problem in embedded/hardware products." > - Head of Embedded, araCreate 3. **Handoff tax** - a board handed to another engineer, or revisited after three weeks, has to be re-understood from scratch. --- ## 02 - Why now: three things became true in the last 18 months. They didn't exist when the incumbents were built. 1. **AI can finally reason over messy hardware data.** LLMs can now read datasheets, schematics, and instrument traces together. *Proof:* an Amazon EE lead built an internal design-checker, injected dozens of errors, and a frontier model caught **100%** when properly guided. 2. **AI can now operate the bench, not just read it.** Agentic tool use almost always points at software tools (MCP servers, APIs). We point it at *physical instruments* - scope, logic analyser, power supply - driven in a loop against the live PCB, captures read back. 3. **The incumbents are from the '90s or earlier.** Altium, Cadence, Rhode & Schwarz, Tektronix, National Instruments - the working paradigm hasn't fundamentally changed in 30 years. The bring-up/debug step has *no* dedicated tool from anyone. > The plumbing now exists, the AI is now good enough, and nobody has wired them together for the engineer at the bench. --- ## 03 - The solution: the one place that holds your design *and* your measurements - and reasons across both. You connect your project (schematic / BOM / firmware) and your bench. Then the agent does what a senior EE does, but instantly and tirelessly: - **Design-aware debugging.** *"This rail should be 3.3 V ±5% per your schematic, but the DMM reads 3.8 V - check R47 and C23."* It knows the intent, so it knows when reality disagrees. - **Cross-instrument correlation.** Scope traces + logic-analyzer decodes + DMM + PSU readings, lined up against the design and firmware state - automatically, not by eyeballing four screens. - **A bring-up journal that writes itself.** Every probe, reading, and conclusion captured as a searchable, time-stamped record - the handoff doc and the compliance artifact, for free. **Works alongside Altium, KiCad, Cadence - not instead of them.** We read your design files; we don't ask you to switch CAD tools. **Why this is the right shape:** - **Reliability is verifiable.** Our output is checkable against an instrument reading. Right or wrong is *measurable*. - **No rip-and-replace.** We sit beside the incumbent CAD tools and the existing bench. Zero switching cost. - **Cross-vendor by design.** Keysight, Tektronix, Siglent, Rigol, Saleae - one agent across all of them. --- ## 04 - The founder: for 15 years I've either been at this bench myself or leading the teams doing the work. **Tom Elliot - Founder** - **Built the industry's first all-day, wrist-worn heart-rate sensor at Fitbit** - the lowest-power PPG sensor of its time. Took it from R&D to the factory line in **Fitbit Surge**; **Sensor Systems Lead** for **Fitbit Ionic**. *I have personally lived hundreds of hours of the bring-up and debug pain this solves.* - **Led hardware teams from IoT to industrial products:** Head of Hardware Engineering at **INFARM**, Head of Engineering at **Senic**. Coached teams to ship reliably - I know how hardware orgs actually work and buy. - **Bootstrapped B2B SaaS for 3 years**, with a consistent income stream the last 18 months. I've honed product, sales, and software-engineering chops the hard way - under real operating constraints. **Why me, specifically:** - **Domain credibility customers trust on day one.** I've sat where my users sit. They open the door because I speak their language, not a pitch. - **I run the company the way the product thinks - AI-native by design.** Agents already do the work a team would - customer-discovery synthesis, research, ops, and engineering, orchestrated through OpenClaw, Claude Code, and whatever comes next. Smallest possible team, **compute over headcount.** --- ## 05 - Validation: the pain is real, the buyers are senior, and the pull is already there. **From the bench (customer discovery):** - A Berlin embedded lead (araCreate) runs board bring-up *"purely manual, with an oscilloscope"* and hand-keeps a "bugs and fixes" log - *"the most crucial part is how I fixed it; the issue recurs after six months and I can't remember."* He has already built his own driver loops to pull readings off his bench instruments (Rigol et al.) for one-off projects and is *"trying to make it work generically."* He is building coscope himself, without us. (*"Single source of truth is the biggest problem in hardware."*) - An EE at a 7-EE audio hardware team (Teufel, ~12 products/yr) takes notes on **"everything"** during bring-up, and - unprompted - described our exact core loop: he wants AI to **review his logic-analyzer I²C streams and work out where it went wrong.** In his board-spin tracker, most issues originate in debug/bring-up. **Proof the approach works:** - An **Amazon EE lead** built an internal AI design-checker, injected dozens of errors. A frontier model caught **100%**. He secured **VP-level budget** to build it in-house. Big companies are validating the thesis with their own money. --- ## 06 - Market & value: we sell time back to the most expensive engineers in the building. **Bottom-up logic (the number that matters):** - A senior EE costs **$150–300/hr** fully loaded. - Bring-up & debug is a **gating, weeks-long** step on every board revision; the early revs alone run **20–40 hours each**. - Across a year that's a few hundred senior-EE hours - **$25k–90k of one engineer's time**, in a phase with no dedicated tool. → *Wedge ACV is a per-seat number anchored to that labour, not to a CAD licence.* **Beachhead → expansion:** - **Beachhead:** well-funded **robotics & hardware startups** (Foundation, Bedrock, Mytra, et al.) and **product teams / consultancies** shipping in a hurry - they feel bring-up pain weekly and move fast on tools. - **Expand:** the EDA tools market alone is **~$10B/yr** (Altium + Cadence), sitting on top of a **~$40B** engineering-tools market - the *direction of travel* once the wedge lands. **Why now, structurally:** AI is driving a proliferation of new hardware products. More boards, brought up faster, by leaner teams - exactly the workflow we serve. --- ## 07 - Competitive landscape: the AI-EDA wave is all aimed at *designing* the board. Nobody is at the bench *after* it's built. | Where the money is going | Players (funding) | What they do | Why it's not us | |---|---|---|---| | **Prompt-to-hardware** (for beginners) | Schematik ($4.6M, Lightspeed-led), Atech ($800K, Sequoia · a16z · Lovable) | Plain-English idea → code, wiring, modules, first prototype | Idea→first prototype, not bring-up/debug of a real board | | Physics-driven **layout** | Quilter ($40M) | Autonomous PCB placement & routing | Pre-fabrication design; not schematic gen, not bring-up | | Browser **AI copilots** | Flux (~$49M), Allspice, Circuit Mind | In-browser design + chat copilot | "Debug" = pasting a scope screenshot; not instrument-integrated | | **Code-as-source** EDA | JITX, atopile, tscircuit, Diode | Define hardware in code | A new design front-end; doesn't touch the bench | | Incumbents | Cadence (Allegro X AI), Siemens, Altium | AI folded into 30-yr-old suites | System-level design + simulation; not the cross-vendor bench | **The bring-up/debug wedge is open.** Nobody is shipping a closed-loop, design-aware, cross-instrument agent. **Our defensibility:** - **Cross-vendor & design-aware from day one** - the one thing single-instrument copilots structurally can't be. - **A proprietary data flywheel:** every bring-up session - design intent paired with real measured outcomes - is training data nobody else is collecting. > "Won't the scope vendors just add their own AI?" They will - and it'll be single-instrument and brand-locked. Real benches are mixed-vendor. The opening is precisely where a Keysight copilot can't go: across all your instruments, tied to your design. --- ## 08 - Business model: start as per-seat SaaS. Grow into the hardware the software runs on. **Today - software, priced against the labour we save:** - **Model:** per-seat subscription for each engineer at the bench. Land with the lead EE, expand across the hardware team. - **Pricing logic:** we save a $150–300/hr engineer meaningful hours every month. A four-figure annual seat is a rounding error - **the ROI argues itself.** - **Reference point:** hardware-in-the-loop tools already sell at **~$5k/year** (per our discovery) - buyers pay real money for this category. - **Why it works:** pure software, no hardware COGS, lands in the **labour budget** - the largest, least-defended budget in the building - not the contested per-seat CAD-licence line. **The arc - software opens the market, hardware is the long-term moat:** > As AI drives the cost of software toward zero, code stops being defensible. The durable advantage is the bench itself - our own debug & capture hardware, designed around the agent. When every competitor can ship the software, the hardware is what drives adoption and retention. - Software lands us in every hardware team; owning the instruments the agent runs on is what keeps us there. - **The moat:** a closed software-defined-instrument loop an incumbent scope vendor can't copy without rebuilding their software, and a SaaS competitor can't copy without building hardware. It's also the definitive answer to the "won't Keysight add AI?" threat (slide 07). --- ## 09 - The ask: raising a $500k pre-seed on a rolling SAFE to prove the wedge with paying design partners. **The round** - **Target:** ~**$500k** pre-seed - **Instrument:** **Rolling SAFE** (single cap, uncapped tranches) - angel checks **≤ $250K**, founder-friendly and fast to close. - **Stage:** first investor conversations - investment window is mid-July to mid-August - **Why $500k goes far:** AI-native inside and out - **compute over headcount.** Tokens are the largest cost (not salaries), so this round behaves like a bigger one - and that cost line is falling fastest in the whole economy. **What it buys - 12 months to a priced seed:** 1. **Ship the MVP** that closes the schematic ↔ firmware ↔ instrument loop on real benches. 2. **Get 3+ design partners paying** - a cheque is the proof the pain is real and their engagement is genuine. 3. **Prove the wedge segment** (funded robotics/aerospace teams). 4. **Automate internal ops.** **What I want from *you*, beyond the cheque:** - Intros to **hardware teams** (robotics, aerospace, consumer EE) for design partners. - Conviction that **hardware development is about to accelerate like software did** - and that coscope is the tooling layer for it.